Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a redundancy operation of a semiconductor memory device.
A semiconductor device may operate abnormally when defects occur in some memory cells of the semiconductor device. In order to address this concern, extra memory cells are made in advance and used to replace cells which are detected as failed cells through a test. In this case, the extra memory cells are referred to as spare cells, and a circuit involved in the replacement operation is referred to as a redundancy circuit.
A failed memory cell is detected through a test and a programming operation which changes an address corresponding to the failed memory cell to an address of a spare cell is performed in an internal circuit. Accordingly, it is necessary to perform an operation of determining whether a normal address inputted during an actual operation of a semiconductor device is an address corresponding to a failed memory cell line.
That is, when it is determined that the inputted normal address is the address corresponding to the failed line, a redundancy line corresponding to a spare cell is selected, instead of the failed line corresponding to the normal address. On the other hand, when it is determined that the inputted normal address is not the address corresponding to the failed line, a normal line corresponding to the normal address is selected.
In this case, a fuse set is generally used to determine whether the inputted normal address is the address corresponding to the failed line. That is, the fuse set is previously set such that it corresponds to the address of the failed line, and it is determined whether the normal address is the address corresponding to the failed line by applying the normal address to the fuse set.
FIG. 1 is a block diagram of a circuit for performing a redundancy operation in a conventional semiconductor memory device.
Referring to FIG. 1, cell arrays provided in the conventional semiconductor memory device may be classified as follows.
A normal cell array is classified into a first normal cell array 10 and a second normal cell array 12. The first normal cell array 10 includes normal cells corresponding to normal odd word lines SWL1 and SWL5 and bit lines BL0 and BL1, and normal cells corresponding to normal even word lines SWL0 and SWL4 and bit lines bar BLB0 and BLB1. The second normal cell array 12 includes normal cells corresponding to normal odd word lines SWL3 and SWL7 and bit lines bar BLB0 and BLB1, and normal cells corresponding to normal even word lines SWL2 and SWL6 and bit lines BL0 and BL1.
Likewise, a redundancy cell array is classified into a first redundancy cell array 14 and a second redundancy cell array 16. The first redundancy cell array 14 includes redundancy cells corresponding to redundancy odd word lines RSWL1 and RSWL5 and bit lines BL0 and BL1, and redundancy cells corresponding to redundancy even word lines RSWL0 and RSWL4 and bit lines bar BLB0 and BLB1. The second redundancy cell array 16 includes redundancy cells corresponding to redundancy odd word lines RSWL3 and RSWL7 and bit lines bar BLB0 and BLB1, and redundancy cells corresponding to redundancy even word lines RSWL2 and RSWL6 and bit lines BL0 and BL1.
Since the normal cell array is classified into the first normal cell array 10 and the second normal cell array 12 and the redundancy cell array is classified into the first redundancy cell array 14 and the second redundancy cell array 16, a repair target word line and one word line adjacent to the repair target word line can be replaced with corresponding redundancy word lines at the same time. Therefore, a repair operation can be performed through an efficient decoding operation for selecting a repair target address.
For example, when a fail occurs in the third normal odd word line SWL3 among the normal odd word lines SWL1, SWL3, SWL5 and SWL7 included in the normal cell array and thus it becomes a repair target word line, the third normal odd word line SWL3 and the fourth word even line SWL4 may be replaced with the redundancy word lines included in the redundancy cell array at the same time, even though the fourth normal even word line SWL4 is in a normal state.
The above-described method in which the normal word line adjacent to the repair target word line is also replaced in order to perform the repair operation through the efficient decoding operation for selecting the repair target address can be performed without any concern in a normal mode operation of the semiconductor memory device.
However, the above-described method may cause a following concern in a test mode operation.
At the test mode operation, the normal word lines SWL1, SWL2, SWL5 and SWL6 corresponding to the cells coupled to the bit lines BL0 and BL1 of the normal cell array 10 or the normal word lines SWL0, SWL3, SWL4 and SWL7 corresponding to the cells coupled to the bit lines bar BLB0 and BLB1 of the normal cell array 10 are only enabled.
In such a test operation, in case where a fail occurs in the word line included in the first normal cell array 10 but a repair operation is performed using the word line included in the second redundancy cell array 16, a test repair operation may be abnormally performed.
That is, in the first normal cell array 10, the cells are formed by the coupling between the normal odd word lines SWL1 and SWL5 and the bit lines BL0 and BL1 or the coupling between the normal even word lines SWL0 and SWL4 and the bit lines bar BLB0 and BLB1. On the other hand, in the second redundancy cell array 16, the cells are formed by the coupling between the redundancy odd word lines RSWL3 and RSWL7 and the bit lines bar BLB0 and BLB1 or the coupling between the redundancy even word lines RSWL2 and RSWL6 and the bit lines BL0 and BL1. Therefore, in case where a fail occurs in the word line included in the first normal cell array 10 but a repair operation is performed using the word line included in the second redundancy cell array 16, the cells coupled to the normal odd word lines SWL1 and SWL5 and the normal even word lines SWL0 and SWL4 of the first normal cell array 10 and the cells coupled to the redundancy odd word lines RSWL3 and RSWL7 and the redundancy even word lines RSWL2 and RSWL6 of the second redundancy cell array 16 are matched with respect to the bit lines BL0 and BL1 and the bit lines bar BLB0 and BLB1 opposite to one another. Thus, the test repair operation may be abnormally performed.
For example, when a fail occurs in the zeroth normal word line SWL0 among the normal word lines SWL0, SWL1, SWL4 and SWL5 included in the first normal cell array 10 and thus it becomes a repair target word line, the first normal word line SWL1 among the normal word lines SWL0, SWL1, SWL4 and SWL5 included in the first normal cell array 10 is to be replaced since one word line adjacent to the repair target word line is also replaced. At this time, if the repair operation is performed using the redundancy word lines RSWL2, RSWL3, RSWL6, and RSWL7, the redundancy word line corresponding to the zeroth normal word line SWL0 is the second redundancy word line RSWL2 or the sixth redundancy word line RSWL6.
In this case, while the zeroth normal word line SWL0 included in the first normal cell array 10 is coupled to the cell in correspondence to the bit lines bar BLB0 and BLB1, the second redundancy word line RSWL2 or the sixth redundancy word line RSWL6 included in the second redundancy cell array 16 is coupled to the cell in correspondence to the bit lines BL0 and BL1. Thus, the cells are matched with respect to the bit lines BL0 and BL1 and the bit lines bar BLB0 and BLB1 opposite to one another.
When the above-described test operation is performed, the first normal word line SWL1 corresponding to the cells coupled to the bit lines BL0 and BL1 may be replaced with the third redundancy word line RSWL3 corresponding to the cells coupled to the bit lines bar BLB0 and BLB1, and the zeroth normal word line SWL0 corresponding to the cells coupled to the bit lines bar BLB0 and BLB1 may be replaced with the second redundancy word line RSWL2 corresponding to the cells coupled to the bit lines BL0 and BL1. Thus, the test fails because the redundancy word lines is not enabled through the test operation.
Therefore, in the prior art, when the method of replacing the repair target word line and the adjacent word line at the same time in order to perform the repair operation through the efficient decoding operation for selecting the repair target address is applied to the above-described test operation, the first normal cell array 10 is controlled such that the repair operation is performed with only the first redundancy cell array 14, and the second normal cell array 12 is controlled such that the repair operation is performed with only the second redundancy cell array 16. However, it is inefficient because the target range of the repair operation is reduced by half for the test operation.